1. Field of the Invention
The present invention relates to a method for forming metal line of a semiconductor device and, more particularly, to a method for forming metal line of a semiconductor device in which, if the aspect ratio of the contact holes is big, contact holes are buried with a CVD method using the HDP method, and the line process is simplified to improve the reliability.
2. Discussion of the Related Art
In an MOS (metal oxide semiconductor) device, the electrode line technology is divided into aluminum lines for formation of gate electrodes, contacting of mutual connection of cells and source/drain impurity diffusion regions.
The characteristic of electrode line depends on 1/K reduction of power voltage and a size of a device according to scaling rule. For example, if a resistance is increased by K times with regard to a gate electrode, a delay time of signal transmission is increased. As a result, the speed of device operation is lowered.
If a resistance is increased by K.sup.2 times with regard to contact holes, the density of current is increased by K times, thereby deteriorating the reliability of lines.
If a resistance is increased by K times with regard to lines, the density of current is increased by K times, thereby causing the deterioration of line reliability by electromigration.
Further, a gate electrode is made of an identical material with word lines of a memory. The material has a low resistivity.
Particularly, as design rule becomes submicronized, line resistance is increased and line pitch is reduced. Accordingly, caused is a problem of delay of RC transmission due to the increase of capacitance.
In case that the design size is less than 1 .mu.m, due to the problem of delay of RC transmission and miniaturization of design rule, the operation speed increased by high integration is not effected and the reliability becomes poor if a gate electrode is made of polysilicon. It is because resistivity of doped polysilicon is higher than 200 .mu..OMEGA..cm. A WSix film, having a relatively good characteristic of step coverage and a resistivity of about 100 .mu..OMEGA..cm, is deposited on polysilicon to be used as an electrode in order to reduce resistance. In other words, a polycide (polysilicon+refractory silicide) is used as an electrode. However, if the line width is less than 0.5 .mu.m according to design rule, the effect of a WSix film having a resistivity of about 100 .mu..OMEGA..cm is in vain.
In order to solve this problem, research and development is actively directed to tungsten having a resistivity of less than 10 .mu..OMEGA..cm, TiSi.sub.2 having a resistivity of less than 20 .mu..OMEGA..cm, COSi.sub.2. having a resistivity of less than 20 .mu..OMEGA..cm, and TiN having a resistivity of less than 30 .mu..OMEGA..cm.
As a higher integration after another has been accomplished, an aspect ratio of a contact hole is abruptly increased. Accordingly, it is required to improve the characteristic of step coverage in burying a contact hole.
In one of methods suggested for improving the step coverage characteristic, tungsten is deposited with a CVD method and etched-back to form a tungsten plug in a contact hole. Then a metal line made of, e.g., aluminum is formed on the tungsten plug. Aluminum used as line metal has such advantages as excellent adhesion with SiO.sub.2, good conductivity, high degree of purity, excellent electric contact with silicon, and facility in patterning. On the other hand, aluminum has a problem of electromigration. If current density of aluminum line is heightened during circuit operation, aluminum atoms are moved. When heat is generated by current, the aluminum line is disconnected by a long-time usage. However, this problem is solved by repeatedly overlapping aluminum on plug formed in a contact hole, or by mixing 4% of copper, or by forming an aluminum line having a uniform thickness.
A background art method for forming a metal line of a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A to 1H are cross-sectional views showing process steps of a background art method for forming a metal line of a semiconductor device.
Referring to FIG. 1A, an isolation oxide film 2 is formed on a predetermined area of a semiconductor substrate 1 so that field and active regions are defined. A gate insulating film 3 and a gate electrode 4 are formed on the semiconductor substrate 1 of the active region. Sidewall spacers 5 are formed on both sides of the gate electrode 4. Next, an ion-implanting process is performed with the gate electrode 4 and the sidewall spacers 5 serving as masks, thereby forming source/drain regions 6 having an LDD (lightly doped drain) structure beneath the surface of the semiconductor substrate 1 at both sides of the gate electrode 4. A refractory metal layer 7 is formed on the gate electrode 4 for improved performance of the gate electrode 4 (low resistance).
Referring to FIG. 1B, an oxide film 8 is formed on the entire surface of the semiconductor substrate 1 including the gate electrode 4.
Referring to FIG. 1C, a BPSG layer 9 is formed on the oxide film 8.
Referring to FIG. 1D, a photoresist film PR is coated on the BPSG layer 9 and patterned with an exposure and development proces so that the surface of the BPSG layer 9 over a placement of a contact hole is exposed.
Referring to Fig. 1E, the BPSG layer 9 and the oxide film 8 are selectively etched with the patterned photoresist film PR serving as a mask so that a predetermined area of the source/drain region 6 at one side of the gate electrode 4 is exposed, thus forming a contact hole 10.
Referring to FIG. 1F, the photoresist film PR is removed.
Referring to FIG. 1G, a barrier metal layer 11 made of Ti/TiN is formed on the surface of the BPSG layer 9 including the semiconductor substrate 1 in the contact hole 10. Subsequently, tungsten is deposited on the barrier metal layer 11 and etched-back to remain only in the contact hole 10, thereby forming a tungsten plug 12. The barrier metal layer 11 serves to improve the adhesion of the tungsten plug 12 and the semiconductor substrate 1.
Referring to FIG. 1H, an aluminum layer 13 used as a metal line is sputtered to be formed on the barrier metal layer 11.
FIGS. 2A to 2B are cross-sectional views showing process steps of another background art method for forming a metal line of a semiconductor device. In this method, an MOCVD (metalorganic chemical vapor deposition) method is applied to form a metal line. Thus, the process of forming a tungsten plug is not needed. Aluminum buries a contact hole to form a metal line in this background art method, unlike the first background art method.
Referring to FIG. 2A, an oxide film 8 and a BPSG layer 9 are formed on the entire surface of a semiconductor substrate 1 where a transistor, not shown in the drawing, is formed. Next, they are selectively patterned with a photolithography process and a photo etching process to form a contact hole 10. Thereafter, a barrier metal layer 11 consisting of Ti/TiN is formed on the entire surface of the BPSG layer 9 including the contact hole 10. Then, an aluminum layer 13 is formed on the barrier metal layer 11 with an MOCVD method. Grain and surface of the aluminum layer 13 are fluctuated.
Referring to FIG. 2B, the process of forming the aluminum layer 13 is continuously carried out with an CVD method of thermal decomposition to bury the contact hole 10. At this time, the aluminum layer 13 have many facets on its surface, which is seriously fluctuated.
A background art method for forming a metal line of a semiconductor device has the following problems.
First, since an aluminum layer is formed after forming a tungsten plug on a barrier metal layer in a contact hole, the process is complicated and the production cost is heightened and the productivity is lowered.
Second, though a line-fabricating method is used in which aluminum is buried on a barrier metal layer in a contact hole, a CVD process of thermal decomposition causes the surface of a line layer to have many facets and be fluctuated, and the metal line is unstable and the line reliability is deteriorated.